The invention relates generally to BEOL wiring structures and design structures, and more particularly to BEOL wiring structures that contain on-chip passive elements and to design structures for use with radiofrequency integrated circuits.
Communications systems rely on circuit boards that integrate discrete passive elements, such as high-Q inductors, capacitors, varactors, and ceramic filters, for matching networks, LC tank circuits in voltage controlled oscillators, attenuators, power dividers, filtering, switching, decoupling, and reference resonators. Circuit board dimensions and component counts are being consistently reduced by contemporary designs for circuitry used in mixed signal or high frequency radiofrequency applications found in communications systems. Unfortunately, off-chip passive elements consume a substantial fraction of the total surface area on the circuit board. Consequently, in more compact designs, off-chip passive elements are being replaced by on-chip passive elements.
On-chip passive elements are commonly used in many types of integrated circuits, such as radiofrequency integrated circuits (RFICs). Metal-insulator-metal (MIM) capacitors and thin film resistors represent two types of on-chip passive elements commonly employed in many types of integrated circuits, including RFICs. A two-electrode MIM capacitor is a stacked structure that includes upper and lower conductive plates, which operate as electrodes, and an interplate dielectric layer disposed between the upper and lower conductive plates. A thin film resistor is formed depositing and patterning a resistive material to a desired size and geometrical shape.
Back-end-of-line (BEOL) interconnect structure used to electrically connect the device structures fabricated on the substrate during front-end-of-line (FEOL) processing. A popular method of forming a BEOL interconnect structure is a dual damascene process in which vias and trenches in various dielectric layers are filled with metal in the same process step to create multi-level, high density metal interconnections. In a via-first, trench-last dual damascene processing process, vias are initially formed in a dielectric layer and then trenches are formed in the dielectric layer above the vias. During the etching process forming the trenches, the vias are unfilled. The trenches and vias are filled with metal using a single blanket deposition followed by planarization. In contrast, a single damascene process forms vias and trenches in distinct dielectric layers and then fills them separately with metal.
On-chip MIM capacitors and on-chip resistors are integrated into one of the dielectric layers in a metallization level of the BEOL interconnect structure. The presence of these on-chip passive elements requires the use of an etching process to define vias of multiple different depths in the dielectric layer. Certain vias are taller than other vias because the top plane of the on-chip passive element is above the top plane of the underlying metallization level shared with the on-chip passive element. In a two-electrode MIM capacitor, for example, vias of multiple different depths are defined for use in establishing electrical contacts with the top and bottom conductive plates, which are located at different depths in the dielectric layer, as well as electrical contacts with conductive features in the dielectric layer of an underlying lower level of the interconnect structure.
Conventional MIM capacitors and BEOL-based thin film resistors are commonly composed of refractory materials like tantalum nitride (TaN) and titanium nitride (TiN), which exhibit superior electrical and mechanical properties in comparison with other traditional types of materials. These materials are also commonly available in copper (Cu) BEOL technologies. Overetch is used during via formation to reliably guarantee penetration through etch stop layers incorporated into the device structure. A problem encountered with on-chip passive elements and the need for vias of different depths is that, during overetch, certain vias may penetrate completely through the refractory metal of one or both of the conductive plates of the MIM capacitor or the refractory metal of the shaped object constituting the thin film resistor. If such a punchthrough event occurs, then a circuit reliability problem or even a catastrophic failure resulting in a nonfunctional chip may occur. For example, the conductive plates of a MIM capacitor may be shorted together by the conductor filling a via etched completely through the top conductive plate and interplate dielectric to the bottom conductive plate. As via heights are scaled downwardly, the height difference among the multiple depth vias is reduced. As a result, the sensitivity of the passive elements to overetch may be exacerbated and the passive elements may be more prone to punchthrough events.
Improved device structures are needed for BEOL wiring structures containing on-chip passive elements, such as MIM capacitors or thin film resistors, as well as related design structures for a RFIC, that alleviate problems associated with damage to passive elements caused by overetch of multiple-height vias.